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RC5054A
Programmable Synchronous DC-DC Converter Controller for Low Voltage Microprocessors
Features
* Drives Two N-Channel MOSFETs * Operates from +5V Power Input * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio * Excellent Output Voltage Regulation * TTL Compatible 5 Bit Digital-to-Analog Output Voltage Selection - Wide Range - 1.3VDC to 3.5VDC - 0.1V Binary Steps from 2.1VDC to 3.5VDC - 0.05V Binary Steps from 1.3VDC to 2.1VDC * Power-Good Output Voltage Monitor * Over-Voltage and Over-Current Fault Monitors - Does Not Require Extra Current Sensing Element, Uses MOSFET's RDS(ON) * Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator Programmable from 50kHz to 1MHz
Applications
* Power Supply for Pentium(R), Pentium Pro, PowerPCTM and AlphaTM Microprocessors * High-Power 5V to 3.xV DC-DC Regulators * Low-Voltage Distributed Power Supplies
Description
The RC5054A provides complete control and protection for a DC-DC converter optimized for high-performance microprocessor applications. It is designed to drive two N-Channel MOSFETs in a synchronous-rectified buck topology. The RC5054A integrates all of the control, output adjustment, monitoring and protection functions into a single package. The output voltage of the converter is easily adjusted and precisely regulated. The RC5054A includes a 5-input digitalto-analog converter (DAC) that adjusts the output voltage from 2.1VDC to 3.5VDC in 0.1V increments and from 1.3VDC to 2.1VDC in 0.05V steps. The RC5054A provides simple, single feedback loop, volt-
Block Diagram
VCC
VSEN 110% + POWER-ON RESET (POR)
-
PGOOD
90% + 115% + OVERVOLTAGE 10A OVP SOFTSTART OVERCURRENT 4V SS BOOT UGATE PHASE VID0 VID1 VID2 VID3 VID4 FB COMP GND RT OSCILLATOR D/A CONVERTER (DAC) DACOUT + PWM COMPARATOR GATE CONTROL LOGIC LGATE PGND
-
+ OCSET REFERENCE 200A
-
+
INHIBIT PWM
-
ERROR AMP
Rev. 1.0.2 Alpha is a trademark of Digital Equipment Corporation. Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation.
RC5054A
PRODUCT SPECIFICATION
age-mode control with fast transient response. It includes a 200KHz free-running triangle-wave oscillator that is adjustable from 50KHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 6V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty ratio ranges from 0% to 100%. The RC5054A monitors the output voltage with a window comparator that tracks the DAC output and issues a Power Good signal when the output is within 10%. The RC5054A protects against over-current conditions by inhibiting PWM operation. Built-in over-voltage protection triggers an external SCR to crowbar the input supply. The RC5054A monitors the current by using the RDS(ON) of the upper MOSFET which eliminates the need for a current sensing resistor.
Pin Assignments
RC5054 (SOIC) TOP VIEW
VSEN OCSET SS VID0 VID1 VID2 VID3 VID4 COMP FB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT OVP VCC LGATE PGND BOOT UGATE PHASE PGOOD GND
Pin Definitions
Pin Number Pin Names 1 VSEN Pin Function Description This pin is connected to the converter's output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET. ROCSET, an internal 200A current source (IOCS), and the upper MOSFET onresistance (RDS(ON)) set the converter over-current (OC) trip point according to the following equation:
I OCS * R OCSET I PEAK = --------------------------------------R DS ( ON )
2
OCSET
An over-current trip cycles the soft-start function. 3 4-8 SS VID0-VID4 Connect a capacitor from this pin to ground. This capacitor, along with an internal 10A current source, sets the soft-start interval of the converter. VID0-4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the converter output voltage. It also sets the PGOOD and OVP thresholds. Table 1 specifies DACOUT for the 32 combinations of DAC inputs. COMP and FB are the available external pins of the error amplifier. The FB pin is the inverting input of the error amplifier and the COMP pin is the error amplifier output. These pins are used to compensate the voltage-control feedback loop of the converter. Signal ground for the IC. All voltage levels are measured with respect to this pin. PGOOD is an open collector output used to indicate the status of the converter output voltage. This pin is pulled low when the converter output is not within 10% of the DACOUT reference voltage. Connect the PHASE pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the MOSFET for over-current protection. This pin also provides the return path for the upper gate drive. Connect UGATE to the upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. This pin provides bias voltage to the upper MOSFET driver. A bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N-Channel MOSFET. This is the power ground connection. Tie the lower MOSFET source to this pin.
9 10
COMP FB
11 12
GND PGOOD
13
PHASE
14 15 16
UGATE BOOT PGND
2
PRODUCT SPECIFICATION
RC5054A
Pin Definitions (continued)
Pin Number Pin Names 17 18 19 20 LGATE VCC OVP RT Pin Function Description Connect LGATE to the lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. Provide a 12V bias supply for the chip to this pin. The OVP pin can be used to drive an external SCR in the event of an overvoltage condition. This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200KHz switching frequency is increased according to the following equation:
3.5 x 10 [ KHz x Kohm ] F S = 200kHz + -----------------------------------------------------------R T [ Kohm ]
6
( R T to GND )
Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation:
3 x 10 [ KHz x Kohm ] F S = 200kHz - ------------------------------------------------------R T [ Kohm ]
5
( R T to 12V )
Absolute Maximum Ratings
Min. Power Input Voltage, VIN Supply Voltage, VCC Boot Voltage, VBOOT - VPHASE VCC or I/O Voltage ESD Classification GND -0.3V Max. 6V +13.5V +13.5V VCC + 0.3V Class 2
Recommended Operating Conditions
Min. Supply Voltage, VCC Ambient Temperature Range Junction Temperature Range +12V -10% 0C 0C Max. +12V +10% 70C 125C
Thermal Characteristics
Parameter Thermal Resistance JA SOIC Package SOIC Package
1
Conditions
Min.
Typ. 110 86
Max.
Units C/W C/W
With 3in2 of Copper Plastic Package -65 Soldering 10s
Maximum Junction Temperature Maximum Storage Temperature Range Maximum Lead Temperature
150 150 300
C C C
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
3
RC5054A
PRODUCT SPECIFICATION
Electrical Specifications (Recommended Operating Conditions unless otherwise specified)
Symbol ICC Parameter Nominal Supply Power-On Reset Rising VCC Threshold Falling VCC Threshold Rising VOCSET Threshold Oscillator Free Running Frequency VOSC Ramp Amplitude Initial Voltage Setpoint Error Amplifier DC Gain GBW SR IUGATE IUGATE ILGATE ILGATE Protection Over-Voltage Trip (VSEN/DACOUT) IOCSET IOVP ISS OCSET Current Source OVP Sourcing Current Soft Start Current Upper Threshold (VSEN/DACOUT) Lower Threshold (VSEN/DACOUT) Hysteresis (VSEN/DACOUT) VPGOOD PGOOD Voltage Low VSEN Rising VSEN Falling Upper and Lower Threshold IPGOOD = -5mA VOCSET = 4.5VDC VSEN = 5.5V, VOVP = 0V - 170 60 - 106 89 - - 115 200 - 10 - - 2 0.5 120 230 - - 111 94 - - % A mA A % % % V Gain-Bandwidth Product Slew Rate Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink COMP = 10pF VBOOT - VPHASE = 12V VUGATE - VPHASE = 1V VCC = 12V, VLGATE = 6V VUGATE - VPHASE = 1V - - - 350 - 300 - 88 15 6 500 100 450 100 - - - - - - - dB MHz V/s mA mA mA mA Reference and DAC ILOAD = 0.8A, VOUT = 2.000V 1.980 2.000 2.020 VOUT = 1.550V 1.534 1.550 1.566 V V RT = OPEN RT = Open 185 - 200 1.9 215 - KHz VP-P VOCSET = 4.5V VOCSET = 4.5V - 8.8 - - - 1.26 10.4 - - V V V Test Conditions UGATE and LGATE Open Min. - Typ. 22 Max. - Units mA VCC Supply Current
Gate Drivers
Power Good
4
PRODUCT SPECIFICATION
RC5054A
Functional Description
Initialization
The RC5054A automatically initializes upon receipt of power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias volt-age at the VCC pin and the input voltage (VIN) on the OCSET pin. The level on OCSET is equal to VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft start operation after both input supply voltages exceed their POR thresholds. For operation with a single +12V power source, VIN and VCC are equivalent and the +12V power source must exceed the rising VCC threshold before POR initiates operation.
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON) to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the softstart function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level. An internal 200A current sink develops a voltage across ROCSET that is referenced to VIN. When the voltage across the upper MOSFET (also referenced to VIN) exceeds the voltage across ROCSET , the over-current function initiates a soft-start sequence. The soft-start function discharges CSS with a 10A current sink and inhibits PWM operation. The soft-start function recharges CSS, and PWM operation resumes with the error amplifier clamped to the SS voltage. Should an overload occur while recharging CSS, the soft start function inhibits PWM operation while fully charging CSS to 4V to complete its cycle. Figure 2 shows this operation with an overload condition. Note that the inductor current increases to over 15A during the CSS charging interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 2 is 2.5W. The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET * R OCSET I PEAK = ------------------------------------------R DS ( ON )
4V 2V 0V 15A 10A 5A 0A
Soft Start
The POR function initiates the soft start sequence. An internal 10A current source charges an external capacitor (CSS) on the SS pin to 4V. Soft start clamps the error amplifier output (COMP pin) and reference input (+ terminal of error amp) to the SS pin voltage. Figure 1 shows the soft start interval with CSS = 0.1F. Initially the clamp on the error amplifier (COMP pin) controls the converter's output voltage. At t1 in Figure 1, the SS voltage reaches the valley of the oscillator's triangle wave. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). This interval of increasing pulse width continues to t2. With sufficient output voltage, the clamp on the reference input controls the output voltage. This is the interval between t2 and t3 in Figure 1. At t3 the SS voltage exceeds the DACOUT voltage and the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The PGOOD signal toggles `high' when the output voltage (VSEN pin) is within 5% of DACOUT. The 2% hysteresis built into the power good comparators prevents PGOOD oscillation due to nominal output voltage ripple.
PGOOD (2V/DIV)
Output Inductor
Soft -Start
0V
Time (20ms/DIV)
SOFT-START (1V/DIV) OUTPUT VOLTAGE (1V/DIV)
Figure 2. Over-Current Operation
0V 0V
t1 t2 t3
where IOCSET is the internal OCSET current source (200A typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: * The maximum RDS(ON) at the highest junction temperature. * The minimum IOCSET from the specification table. * Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. 5
Time (5ms/DIV)
Figure 1. Soft Start Interval
RC5054A
PRODUCT SPECIFICATION
For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection.' A small ceramic capacitor should be placed in parallel with ROCSET to smooth the voltage across ROCSET in the presence of switching noise on the input voltage.
Output Voltage Program
The output voltage of a RC5054A converter is programmed to discrete levels between 1.3VDC and 3.5VDC . The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a 5-bit digital-to-analog converter
(DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the 32 combinations of open or short connections on the VID pins. The output voltage should not be adjusted while the converter is delivering power. Remove input power before changing the output voltage. Adjusting the output voltage during operation could toggle the PGOOD signal and exercise the overvoltage protection. Grounding any combination of the VID pins increases the DACOUT voltage.
Table 1. Output Voltage Table
PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 PIN NAME VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 NOMINAL OUTPUT VOLTAGE SHDN 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5
Note: 1. 0 = connected to GND or VSS, 1 = OPEN
6
PRODUCT SPECIFICATION
RC5054A
Typical Application
+12V
VIN = +5V VCC PGOOD SS OVP RT VID0 VID1 VID2 VID3 VID4 FB MONITOR AND PROTECTION OCSET EN BOOT
OSC
UGATE PHASE +VOUT
RC5054
D/A + +
-
LGATE PGND VSEN GND
-
COMP
Applications Discussion
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding. Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board The components shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the RC5054A within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs' gate and source connections from the RC5054A must be sized to handle up to 1A peak current.
VIN
Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS PIN and locate the capacitor, CSS close to the SS pin because the internal current source is only 10A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins.
BOOT CBOOT +VIN D1 Q1 L O VOUT VCC LOAD
RC5054A
SS
PHASE +12V Q2 CO
CSS GND
CVCC
Figure 4. Printed Circuit Board Small Signal Layout Guidelines
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
RC5054A
UGATE PHASE Q2 LGATE PGND D2 Q1 LO
VOUT LOAD
CIN
CO
RETURN
Figure 3. Printed Circuit Board Power and Ground Planes or Islands
7
RC5054A
PRODUCT SPECIFICATION
3.
VIN OSC PWM COMPARATOR DRIVER LO DRIVER PHASE CO ESR (PARASITIC) ZFB VE/A + ERROR AMP VOUT
Place 2ND Zero at Filter's Double Pole Place 1ST Pole at the ESR Zero Place 2ND Pole at Half the Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin - Repeat if Necessary
4. 5. 6. 7.
DVOSC
-
+
Compensation Break Frequency Equations
ZIN REFERENCE
-
1 F Z1 = -------------------------------2 * R2 * C1
1 F P1 = --------------------------------------------------C1 * C2 2 * R2 * -------------------- C1 + C2 1 F P2 = -------------------------------2 * R3 * C3
DETAILED COMPENSATION COMPONENTS C2 C1 R2 ZFB ZIN C3 R1 FB R3 VOUT
1 F Z2 = -------------------------------------------------2 * ( R1 + R3 ) * C3
COMP
+
RC5054
DACOUT
Figure 5. Voltage-Mode Buck Converter Compensation Design
The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break freaquency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC.
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
100 80 60 GAIN (dB) 40 20 0 -20 -40
FLC MODULATOR GAIN FESR 20LOG (R2/R1) 20LOG (VIN /VOSC) COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP ERROR AMP GAIN
Modulator Break Frequency Equations
1 F LC = -----------------------------------2 * L O * C O 1 F ESR = -----------------------------------2 * ESR * C O
FZ1 FZ2
FP1
FP2
The compensation network consists of the error amplifier (internal to the RC5054A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 5. Use these guidelines for locating the poles and zeros of the compensation network: 1. 2. Pick Gain (R2/R1) for desired converter bandwidth Place 1ST Zero Below Filter's Double Pole (~75% FLC)
-60
10
100
1K
10K 100K 1M FREQUENCY (Hz)
10M
Figure 6. Asymptotic Bode Plot of Converter Gain
8
PRODUCT SPECIFICATION
RC5054A
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1F ceramic capacitors in the 1206 surface-mount package. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the RC5054A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
L x I TRAN t RISE = ----------------------------V IN - V OUT L x I TRAN tFALL = ------------------------V OUT
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a +5V input source, the worst case response time can be either at the application or removal of load and dependent upon the DACOUT setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. 9
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
V IN - V OUT V OUT I = ----------------------------- * -------------FS x L V IN V OUT = I x ESR
RC5054A
PRODUCT SPECIFICATION
MOSFET Selection/Considerations
The RC5054A requires 2 N-Channel power MOSFETs. These should be selected based upon RDS(ON), gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the Schottky rectifier clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the RC5054A and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW, which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
+12V DBOOT +5V VCC
RC5054A
BOOT CBOOT UGATE PHASE Q1 NOTE: VG-S VCC -VD Q2 D2 NOTE: VG-S VCC
+
-
LGATE PGND GND
Figure 7. Upper Gate Drive - Bootstrap Option
Figure 8 shows the upper gate drive supplied by a direct connection to VCC. This option should only be used in converter systems where the main input voltage is +5VDC or less. The peak upper gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
+12V
P LOWER =
2 IO
x R DS ( ON ) x ( 1 - D )
VCC
+5V OR LESS
1 2 P UPPER = I O x R DS ( ON ) x D + -- Io x V IN x t SW x F S 3 RC5054A
BOOT Q1 NOTE: VG-S VCC -5V Q2 D2 NOTE: VG-S VCC
Where: D is the duty cycle = VOUT/VIN, tSW is the switching interval, and FS is the switching frequency Standard-gate MOSFETs are normally recommended for use with the RC5054A. However, logic-level gate MOSFETs can be used under special circumstances. The input voltage, upper gate drive level, and the MOSFET's absolute gateto-source voltage rating determine whether logic-level MOSFETs are appropriate. Figure 7 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC. The boot capacitor, CBOOT develops a floating supply voltage referenced to the PHASE pin. This supply is refreshed each cycle to a voltage of VCC less the boot diode drop (VD) when the lower MOSFET, Q2 turns on. Logic-level MOSFETs can only be used if the MOSFET's absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC.
+
UGATE PHASE
LGATE PGND GND
Figure 8. Upper Gate Drive - Direct VCC Drive Option
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower MOSFET and turning on the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency will drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage.
10
PRODUCT SPECIFICATION
RC5054A
RC5054A DC-DC Converter Application Circuit
Figure 10 shows an application circuit of a DC-DC Converter for an Intel Pentium Pro microprocessor.
F1 VIN = +5V
L1 - 1H
C1 5x 1000F
+12V 2N6394 47 2K
2x 1F
1 F 1000pF VCC 18 SS 3 0.1F VSEN 1 RT VID0 VID1 VID2 VID3 VID4 FB 20 4 5 6 7 8 10 OSC OVP 19 2 OCSET 12 PGOOD 15 BOOT 1K
MONITOR AND PROTECTION
14 UGATE 4.7 13 PHASE
Q1
RC5054A
D/A
L2 3H
+VO
+
+ 9 11 COMP
17 LGATE 4.7 16 PGND GND
Q2
D1
-
CO 9x 1000F
2.2nF 8.2nF 0.1F 1.33K 15 20K
Component Selection Notes; C0 - 9 Each 1000F 6.3W VDC, Sanyo MV-GX or Equivalent C1 - 5 Each 1000F 25W VDC, Sanyo MV-GX or Equivalent L2 - Core: Micrometals T50-52B; Each Winding: 10 Turns of 16AWG L1 - Core: Micrometals T50-52; Winding: 5 Turns of 18AWG D1 - 3A, 40V Schottky, Motorola MBR340 or Equivalent Q1, Q2 - Fairchild FDB6030L
Figure 9. Pentium Pro DC-DC Converter
11
RC5054A
PRODUCT SPECIFICATION
Mechanical Dimensions (20 Lead SOIC)
Symbol A A1 B C D E e H h L N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals.
.093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC .394 .010 .016 20 0 -- 8 .004 .419 .029 .050
2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC 10.00 0.25 0.40 20 0 -- 8 0.10 10.65 0.75 1.27
3 6
20
11
E
H
1
10
D A e B A1 SEATING PLANE -C- LEAD COPLANARITY ccc C
h x 45 C
L
12
RC5054A
PRODUCT SPECIFICATION
Ordering Information
Part Number RC5054AM Temperature Range (C) 0 to 70 Package 20 Ld SOIC
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 8/11/99 0.0m 004 Stock#DS30005054 (c) 1998 Fairchild Semiconductor Corporation

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